As semiconductor device integration continues to advance, device geometries continue to shrink. Smaller device geometries require thinner thin film layers used in the manufacture of those devices, including thinner dielectric layers. As device density becomes greater and dielectric layers become thinner, inter-level parasitic capacitance becomes an increasingly significant problem in terms of device performance.
Prior art approaches to reduce parasitic capacitance include the use of low permittivity or so-called low k dielectric materials. Typically, materials having a permittivity value below that of silicon oxide (SiO2), i.e., about 3.9, are termed low k dielectrics. Such low k dielectrics used in lieu of traditional dielectric materials can lessen the capacitance between, e.g., metal interconnects.
Low k dielectrics suffer from several disadvantages, however. One of the foremost disadvantages is that low k dielectric materials tend to have poor mechanical properties, such as poor adhesion and poor mechanical strength. These shortcomings result in diminished device yield, reliability, and overall performance.
What is needed, therefore, is a low k dielectric material that overcomes the mechanical shortcomings of traditional low permittivity dielectrics.